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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit pd98421 high-speed address search engine 1998 ? document no. s13650ej5v0ds00 (5th edition) date published january 2002 ns cp (k) printed in japan data sheet the mark shows major revised points. description the pd98421 is a cam (content addressable memory) with a capacity of 64 bits 8192 entries. equipped with three types of search modes, this memory can search data at high speeds. one of these search modes, longest prefix match mode, can mask data in entry units and output the address with the longest match in the search data. this function is effective for searching ip addresses of layer 3. features ? 64 bits 8k entries ? high-speed synchronous operation. maximum operating frequency: 33 mhz (normal mode)/50 mhz (ff mode) ? mask register masking any bit of 64-bit search data ? three search modes supported for high-speed searching. ? full match mode: 30 ns (at 33 mhz) full match with mask mode: 30 ns longest prefix match mode: 60 ns ? number of entries can be expanded by connecting multiple pd98421s. ? can read/write data by high-speed synchronous operation (memory operation). ? supply voltage: 3.3 v 0.15 v ? 240-pin plastic fbga ordering information part number package pd98421f1-ga1 240-pin plastic fbga (16 16) remark in this document, active-low pins are expressed as xxx_b (_b suffixed to a pin name).
data sheet s13650ej5v0ds 2 pd98421 block diagram clk sequencer block search data register bus i/f block memory block search mask data register mode register search engine block mask data memory (64 bits 4096 words) entry data memory (64 bits 4096 words) reset_b ce ce_b wait_b had0 to had12 hit_b err_b full fmsk v dd gnd enhit_b smd63 to smd0 a12 to a0 data63 to data0 we_b oe_b mem
data sheet s13650ej5v0ds 3 pd98421 system configuration example sram_ce router lsi synchronous sram v dd ce_b, ce a14 to a0 data63 to data0 oe_b, we_b pd98421 #0 ce_b, ce enhit_b hit_b smd63 to smd0 had12 to had0 err_b mem, full, fmsk a12 to a0 data63 to data0 oe_b, we_b pd98421_ce0 pd98421_ce1 mem, full, fmsk oe_b, we_b data63 to data0 a14 to a0 pd98421 #1 ce_b, ce enhit_b hit_b smd63 to smd0 had12 to had0 err_b mem, full, fmsk a12 to a0 data63 to data0 oe_b, we_b pd98421 #n ce_b, ce enhit_b hit_b smd63 to smd0 had12 to had0 err_b mem, full, fmsk a12 to a0 data63 to data0 oe_b, we_b pd98421_cen hit_b hit address12 to 0 err_b hit address14, 13 hitout_b errout_b hadout hit_bn enhit_bn hit_b1 enhit_b1 hit_b0 enhit_b0 glue logic
data sheet s13650ej5v0ds 4 pd98421 pin configuration ? ? ? ? 240-pin plastic fbga (16 16) 35 pd98421f1-ga1 (bottom view) 36 37 38 39 40 41 42 43 44 45 50 46 47 48 49 51 52 34 99 100 101 102 103 104 105 106 107 108 113 109 110 111 112 114 53 33 98 155 156 157 158 159 160 161 162 163 168 164 165 166 167 115 54 32 97 154 203 204 205 206 207 208 209 210 169 211 212 213 214 116 55 31 96 153 202 30 95 152 201 29 94 151 200 28 93 150 199 27 92 149 198 91 148 197 25 90 147 196 24 89 146 195 26 232 231 230 229 23 88 145 194 22 87 144 193 21 86 143 192 20 85 142 141 19 84 83 82 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 133 132 131 130 129 128 140 139 138 137 136 135 134 181 180 127 66 224 179 126 65 64 223 178 125 222 177 124 63 221 176 123 62 61 220 175 122 219 174 121 60 218 173 120 59 58 217 172 119 240 239 238 237 170 215 117 56 171 216 118 57 184 183 182 191 190 189 188 187 186 185 228 227 226 225 233 234 235 236 v u t r p nml k j h g e f d c b a 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 index mark index mark pd98421f1-ga1 (top view)
data sheet s13650ej5v0ds 5 pd98421 pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 (a1) l 49 (d18) data23 97 (u15) gnd 145 (t6) gnd 193 (r5) data38 2 (b1) l 50 (c18) smd22 98 (u16) a3 146 (t7) gnd 194 (r6) data40 3 (c1) i.c. 51 (b18) data21 99 (u17) v dd 147 (t8) smd36 195 (r7) smd38 4 (d1) data63 52 (a18) smd20 100 (t17) a1 148 (t9) data34 196 (r8) data35 5 (e1) gnd 53 (a17) v dd 101 (r17) had12 149 (t10) data32 197 (r9) gnd 6 (f1) data60 54 (a16) data18 102 (p17) gnd 150 (t11) we_b 198 (r10) smd32 7 (g1) smd59 55 (a15) data17 103 (n17) had6 151 (t12) mem 199 (r11) oe_b 8 (h1) data57 56 (a14) gnd 104 (m17) had3 152 (t13) gnd 200 (r12) ce_b 9 (j1) v dd 57 (a13) smd15 105 (l17) gnd 153 (t14) a9 201 (r13) a12 10 (k1) smd55 58 (a12) smd13 106 (k17) enhit_b 154 (t15) a6 202 (r14) a8 11 (l1) smd53 59 (a11) v dd 107 (j17) smd30 155 (t16) a4 203 (r15) a0 12 (m1) gnd 60 (a10) smd10 108 (h17) data28 156 (r16) had11 204 (p15) gnd 13 (n1) smd50 61 (a9) smd9 109 (g17) data26 157 (p16) had9 205 (n15) v dd 14 (p1) data48 62 (a8) data7 110 (f17) data25 158 (n16) had7 206 (m15) had4 15 (r1) gnd 63 (a7) gnd 111 (e17) gnd 159 (m16) had2 207 (l15) hit_b 16 (t1) data46 64 (a6) smd4 112 (d17) gnd 160 (l16) v dd 208 (k15) smd31 17 (u1) data45 65 (a5) smd3 113 (c17) data20 161 (k16) reset_b 209 (j15) v dd 18 (v1) smd44 66 (a4) gnd 114 (b17) gnd 162 (j16) gnd 210 (h15) gnd 19 (v2) gnd 67 (a3) data0 115 (b16) data19 163 (h16) smd28 211 (g15) v dd 20 (v3) data42 68 (a2) v dd 116 (b15) smd18 164 (g16) smd26 212 (f15) smd24 21 (v4) gnd 69 (b2) gnd 117 (b14) data16 165 (f16) smd25 213 (e15) data22 22 (v5) smd40 70 (c2) i.c. 118 (b13) data15 166 (e16) smd23 214 (d15) smd19 23 (v6) smd39 71 (d2) v dd 119 (b12) gnd 167 (d16) v dd 215 (d14) data14 24 (v7) data37 72 (e2) data62 120 (b11) smd12 168 (c16) smd21 216 (d13) smd16 25 (v8) gnd 73 (f2) smd61 121 (b10) smd11 169 (c15) gnd 217 (d12) smd14 26 (v9) smd34 74 (g2) gnd 122 (b9) data8 170 (c14) smd17 218 (d11) data11 27 (v10) data33 75 (h2) smd58 123 (b8) smd7 171 (c13) v dd 219 (d10) data9 28 (v11) clk 76 (j2) data56 124 (b7) smd5 172 (c12) data13 220 (d9) gnd 29 (v12) wait_b 77 (k2) data54 125 (b6) v dd 173 (c11) gnd 221 (d8) smd6 30 (v13) ce 78 (l2) data52 126 (b5) smd2 174 (c10) data10 222 (d7) gnd 31 (v14) n.c. 79 (m2) smd51 127 (b4) smd0 175 (c9) smd8 223 (d6) data2 32 (v15) a10 80 (n2) data49 128 (b3) l 176 (c8) data6 224 (d5) smd1 33 (v16) a7 81 (p2) v dd 129 (c3) l 177 (c7) data4 225 (h5) data58 34 (v17) a5 82 (r2) smd46 130 (d3) gnd 178 (c6) data3 226 (j5) gnd 35 (v18) a2 83 (t2) data44 131 (e3) smd63 179 (c5) data1 227 (k5) data53 36 (u18) gnd 84 (u2) v dd 132 (f3) data61 180 (c4) gnd 228 (l5) data51 37 (t18) n.c. 85 (u3) data43 133 (g3) data59 181 (d4) l 229 (p8) smd37 38 (r18) had10 86 (u4) smd42 134 (h3) gnd 182 (e4) smd60 230 (p9) v dd 39 (p18) had8 87 (u5) smd41 135 (j3) smd56 183 (f4) smd62 231 (p10) gnd 40 (n18) had5 88 (u6) data39 136 (k3) smd54 184 (g4) v dd 232 (p11) full 41 (m18) had1 89 (u7) v dd 137 (l3) smd52 185 (h4) smd57 233 (l14) had0 42 (l18) err_b 90 (u8) data36 138 (m3) data50 186 (j4) data55 234 (k14) data31 43 (k18) gnd 91 (u9) smd35 139 (n3) smd49 187 (k4) gnd 235 (j14) data29 44 (j18) data30 92 (u10) smd33 140 (p3) data47 188 (l4) v dd 236 (h14) smd27 45 (h18) smd29 93 (u11) gnd 141 (r3) gnd 189 (m4) gnd 237 (e11) data12 46 (g18) data27 94 (u12) fmsk 142 (t3) smd45 190 (n4) smd48 238 (e10) gnd 47 (f18) gnd 95 (u13) v dd 143 (t4) v dd 191 (p4) smd47 239 (e9) v dd 48 (e18) data24 96 (u14) a11 144 (t5) data41 192 (r4) smd43 240 (e8) data5 remarks 1. figures in parentheses indicate the coordinates in the pin configuration. 2. i.c.: internal connection l: fixed at low level n.c.: no connection
data sheet s13650ej5v0ds 6 pd98421 pin names a12 to a0: address ce, ce_b: chip select clk: clock data63 to data0: data enhit_b: enable hit err_b: error fmsk: full match mask mode full: full match mode gnd: ground had12 to had0: hit address hit_b: hit mem: memory oe_b: output enable reset_b: reset smd63 to smd0: search mask data v dd : supply voltage wait_b: wait we_b: write enable
data sheet s13650ej5v0ds 7 pd98421 contents 1. pin functions ............................................................................................................... .................... 8 2. memory/register configuration.......................................................................................... 11 2.1 memory configuration........................................................................................................ ....... 11 2.1.1 full match mode........................................................................................................... ....................11 2.1.2 full match with mask/longest prefix match mode ...........................................................................1 1 2.2 register configuration ...................................................................................................... ........ 12 2.2.1 search data register ...................................................................................................... ...................12 2.2.2 mask data register........................................................................................................ ....................12 2.2.3 mode register ............................................................................................................. ......................13 2.2.4 nop register.............................................................................................................. .......................13 3. functional description...................................................................................................... ...... 14 3.1 memory operation ............................................................................................................ ......... 14 3.2 search operation ............................................................................................................ ........... 14 3.2.1 full match mode........................................................................................................... ....................14 3.2.2 full match with mask mode................................................................................................. .............15 3.2.3 longest prefix match mode................................................................................................. .............17 3.2.4 other points to be noted.................................................................................................. .................19 4. electrical specifications ................................................................................................... .... 21 5. recommended soldering conditions................................................................................. 38 6. package drawing ............................................................................................................. ........... 39
data sheet s13650ej5v0ds 8 pd98421 1. pin functions pin name pin no. i/o description clk 28 input clock. system clock input pin. inputs a clock of up to 33 mhz (normal mode)/50 mhz (ff mode). wait_b 29 input wait. wait input pin. asserted active at low level. if the wait_b signal is active at the rising edge of clk, the pd98421 is placed in a wait status for the duration of 1 clk cycle from the next rising of clk. in wait status, all the pins retain the status immediately before the wait status was set. however, output control by ce, ce_b, and enhit_b is valid. ce_b 200 input chip select. asserted active at low level. when the ce signal and ce_b signal of a chip are asserted active at the same time, the chip is selected. data, had, err_b, and smd of the unselected chip enter a high-impedance state. ce 30 input chip select. asserted active at low level. when the ce signal and ce_b signal of a chip are asserted active at the same time, the chip is selected. data, had, err_b, and smd of the unselected chip enter a high-impedance state. a12 to a0 201, 96, 32, 153, 202, 33, 154, 34, 155, 98, 35, 100, 203 input address. a12 to a0 are 13-bit address signals. signals input to a12 through a8 are ignored in the i/o access mode. data63 to data0 4, 72, 132, 6, 133, 225, 8, 76, 186, 77, 227, 78, 228, 138, 80, 14, 140, 16, 17, 83, 85, 20, 144, 194, 88, 193, 24, 90, 196, 148, 27, 149, 234, 44, 235, 108, 46, 109, 110, 48, 49, 213, 51, 113, 115, 54, 55, 117, 118, 215, 172, 237, 218, 174, 219, 122, 62, 176, 240, 177, 178, 223, 179, 67 i/o data. data63 to data0 are data bus signals that input/output 64-bit data to/from the internal memory and registers. we_b 150 input write enable. enables writing to data63 to data0. when the we_b signal is active, data63 to data0 enter a high-impedance state. oe_b 199 input output enable. enables output of data from data63 to data0.
data sheet s13650ej5v0ds 9 pd98421 pin name pin no. i/o description mem 151 input memory. specifies access right to memory/register. when the mem signal is high, the pd98421 performs the same operations as an sram (refer to 3. functional description ). when this signal is low, the internal registers can be accessed for input/output. mem access function 1 memory access 0 i/o access full 232 input full match mode. sets a search mode with the mem and fmsk signals (refer to 3. functional description ). fmsk 94 input full match with mask mode. sets a search mode with the mem and full signals (refer to 3. functional description). had12 to had0 101, 156, 38, 157, 39, 158, 103, 40, 206, 104, 159, 41, 233 output 3 state (internal pull-up) hit address. had12 through had0 output a matched valid address if the hit_b signal goes low and err_b goes high during a search operation. if err_b is asserted active (low level), had output is invalid. had12 is meaningless except in the full match mode. these pins are internally pulled up. hit_b 207 output hit. data is searched after it is written to the search data register during a search operation. hit_b is a low-active signal that indicates that data matching the search data has been found. 0: match data found, 1: match data not found err_b 42 output (open drain) error. this signal goes low if two or more sets of entry data having the same mask data are found during a search operation. because this is an open-drain signal, pull it up. this signal is inactive (high-impedance) during a memory operation. enhit_b 106 input enable hit. this signal controls output of the had12 to had0 and err_b signals. enhit_b had[12:0] err_b 1hi-z hi-z 0 output enabled smd63 to smd0 131, 183, 73, 182, 7, 75, 185, 135, 10, 136, 11, 137, 79, 13, 139, 190, 191, 82, 142, 18, 192, 86, 87, 22, 23, 195, 229, 147, 91, 26, 92, 198, 208, 107, 45, 163, 236, 164, 165, 212, 166, 50, 168, 52, 214, 116, 170, 216, 57, 217, 58, 120, 121, 60, 61, 175, 123, 221, 124, 64, 65, 126, 224, 127 i/o (internal pull-up) search mask data. the smd63 to smd0 signals are used for temporary i/o with other pd98421s in the longest prefix match mode. connect each of these pins to the corresponding pin of the other pd98421s.
data sheet s13650ej5v0ds 10 pd98421 pin name pin no. i/o description reset_b 161 input reset. when this signal is set to low, the chip is initialized. only the internal sequencer and mode register are initialized; the memory area is not cleared. be sure to create an external circuit in which reset_b becomes low level after power application. in addition, input at least 2 clk or more nop commands continuously after releasing reset. vdd 9, 53, 59, 68, 71, 81, 84, 89, 95, 99, 125, 143, 160, 167, 171, 184, 188, 205, 209, 211, 230, 239 ? 3.3 v power supply gnd 5, 12, 15, 19, 21, 25, 36, 43, 47, 56, 63, 66, 69, 74, 93, 97, 102, 105, 111, 112, 114, 119, 130, 134, 141, 145, 146, 152, 162, 169, 173, 180, 187, 189, 197, 204, 210, 220, 222, 226, 231, 238 ? ground n.c. 31, 37 ? no connection. leave open. i.c. 3, 70 ? internally connected. leave open. l 1, 2, 128, 129, 181 ? always fix these pins at low level.
data sheet s13650ej5v0ds 11 pd98421 2. memory/register configuration 2.1 memory configuration the pd98421 has a memory area of 64 bits 8192 entries. two types of memory configurations can be selected in accordance with the search mode. for this selection, no special setting of the chip is necessary. the pd98421 can also be used as a synchronous sram. 2.1.1 full match mode 64 bits 8192 entries: entry data in the full match mode, all the 8192 entries are used as a data area. table 2-1. memory mapping in full match mode address contents 0000h entry data 0001h entry data :: 0fffh entry data 1000h entry data :: 1ffeh entry data 1fffh entry data 2.1.2 full match with mask/longest prefix match mode 64 bits 4096 entries: entry data 64 bits 4096 entries: entry mask data in the full match with mask and longest prefix match modes, 4096 entries at addresses 0000h to 0fffh are used as a data area, and addresses 1000h to 1fffh are used as a mask data area. the mask data at 1000h to 1fffh mask each of the corresponding entry data as shown in table 2-2. if a bit of the mask data is 0, the corresponding bit of the entry data is ignored during the search. the mask data must be successively masked, starting from the lsb, in the longest prefix match mode. example ffff0000 correct, ff00f000 incorrect
data sheet s13650ej5v0ds 12 pd98421 table 2-2. memory mapping in full match with mask/longest prefix match modes address contents 0000h entry data 0001h entry data :: 0fffh entry data 1000h mask data of 0000h :: 1ffeh mask data of 0ffeh 1fffh mask data of 0fffh 2.2 register configuration the pd98421 allocates the internal registers to 256 words of i/o addresses. each register is 64 bits long. address signal lines a0 through a7 are used to specify an i/o address to access a register. a8 through a12 are not used. when a register is accessed, the mem signal line is made low. to write data to the register, the we_b pin is asserted active; to read data from the register, the oe_b pin is asserted active. data can be written to a register in 1 clock cycle in both the normal and ff modes (except a search operation by writing data to the search data register). when a register is read in the normal mode, the read data is output 1 clock cycle after the i/o address has been input. in the ff mode, the read data is output 2 clock cycles after address input. for the details of the normal and ff modes, refer to 2.2.3 mode register . table 2-3. internal registers i/o address register 00h search data register 01h mask data register 02h mode register 03h reserved (do not access this register.) 04h nop register 05 to ffh reserved (do not access this register.) 2.2.1 search data register the search data is stored in this register. when 64-bit search data is written to the search data register, the pd98421 starts a search operation. the search data register is not initialized even when the chip is reset. 2.2.2 mask data register the mask data register stores a value to mask the search data stored in the search data register. store a valid value in this register before a value is written to the search data register. if a bit of the mask data register is 0, the corresponding bit of the search data register is masked and ignored. the masking specified by this register is valid for all entries in all the search modes. the mask data register is not initialized even when the chip is reset. when the bit width of all entries is less than 64 bits, it is recommended to mask unused bits using this function (to reduce the current consumption of the chip). however, do not mask bit 63.
data sheet s13650ej5v0ds 13 pd98421 2.2.3 mode register the mode register selects the search timing mode (normal/ff mode) of the pd98421 and controls the operations of the pd98421 without using the full, fmsk, and wait_b signal lines. this register is initialized to 0 after the chip has been reset. 63 6543210 reserved ff full fmsk wait_b2 wait_b1 enbl enbl validates or invalidates the full, fmsk, wait_b2, and wait_b1 bits of the mode register. 0: invalidates full, fmsk, wait_b2, and wait_b1 bits, and validates the full, fmsk, and wait_b signal lines. 1: validates full, fmsk, wait_b2, and wait_b1 bits, and invalidates the full, fmsk, and wait_b signal lines. wait_b1 specifies whether a wait cycle is inserted after the first clock. 0: inserts 1 wait cycle after a search operation. in the longest prefix match mode, one wait cycle is inserted between the first search clock and second search clock. 1: no operation wait_b2 specifies whether a wait cycle is inserted after the second clock. 0: inserts one wait cycle after the second search clock in the longest prefix match mode. 1: no operation full, fmsk selects a search mode ([full, fmsk] = [xx]). 00: longest prefix match mode 01: reserved 10: full match mode 11: full match with mask mode ff selects a search timing mode (normal or ff mode). 0: normal mode. the hit address is output one clock after data has been input in the full match or full match with mask mode at up to 33 mhz. in the longest prefix match mode, the hit address is output two clocks after data has been input. 1: ff mode the hit address is output two clocks after data has been input in the full match or full match with mask mode at up to 50 mhz. in the longest prefix match mode, the hit address is output four clocks after data has been input. reserved reserved bit 64 to bit 6 do not access these bits. remark do not execute another operation immediately after write access to the mode register or mask data register. be sure to perform nop (write the nop register) for the duration of at least 1 clock before executing the another operation. 2.2.4 nop register when data is written to the nop register, the pd98421 is in a no-operation status, in which it performs nothing. keep the pd98421 in this status when no operations such as search memory access are being performed. an undefined value is read from the nop register if it is read.
data sheet s13650ej5v0ds 14 pd98421 3. functional description the pd98421 can select an operation mode for memory operation and search operation by using combinations of the mem, full, and fmsk signals, or combinations of the full and fmsk bits. table 3-1. operation modes mem full fmsk function 1 memory operation 0 1 0 full match mode 0 1 1 full match with mask mode 0 0 0 longest prefix match mode 0 0 1 none (setting prohibited) 3.1 memory operation the pd98421 can read or write 64-bit data from or to an internal memory cell during operation, like a synchronous sram. during memory operation, the mem pin is set to high. when data is written, the we_b signal is asserted active; when data is read, the oe_b signal is asserted active. data can be written within 1 clock in both the normal and ff modes. when data is read, the read data is output 1 clock after address input in the normal mode. in the ff mode, the read data is output 2 clocks after address input. note, however, that outputting the read data can be delayed by inserting a wait cycle. 3.2 search operation a search operation is started when a search mode is set and the search data is written to the search data register. a search mode can be set by setting the mem, full, and fmsk signal lines in the search mode (refer to table 3-1 ) or by using the mode register (refer to 2.2.3 mode register ). 3.2.1 full match mode in the full match mode, data that completely matches is searched. in this mode, entry data of 8k entries and one mask register can be used. to search data in the full match mode, set the signal lines as shown in table 3-1 (or set the mode register), and write the search data to the search data register. the value of the search data register is masked by the value of the mask data register and compared with the 64- bit value of 8k words of memory cells. the bit of the search data register corresponding to a bit of the mask data register that is set to 0 is not used for comparison. one clock after the search data has been written to the search data register in the normal mode (in the ff mode, two clocks after), the hit_b signal is asserted active. the address of the match data is output to had12 to had0 if enhit_b is set to 0. if two or more match data items are found during the search operation, err_b goes low, and the output to had12 to had0 is invalid. the timing to output the hit address can be delayed by inserting wait_b. when the enhit_b signal is set to 1, err_b and had12 to had0 enter a high-impedance state.
data sheet s13650ej5v0ds 15 pd98421 example to search the data in table 3-2 from the data shown in table 3-3 in the full match mode (for the sake of convenience, 64-bit values are indicated in hexadecimal form in units of 8 bits). because bits 40 to 47 and 8 to 15 of the mask data register in table 3-2 are 0, the data of the corresponding bits of the search register (44 and 77) is not compared when the data of memory cells is compared. bits 40 to 47 (abh) and 8 to 15 (78h) of the data stored in 0003h are different from the values of the search data register, but this is ignored depending on the mask data register setting. all the other bits match the values of the search data register. this data is match data, and address 0003h is the match address. table 3-2. example of search data search data register mask data register 11.22.33.44.55.66.77.88 ff.ff.00.ff.ff.ff.00.ff table 3-3. example of data address data 0000h ff.ff.ff.ff.ff.ff.ff.ff. 0001h 11.11.22.33.44.55.66.77 0002h 11.22.33.44.55.66.77.99 0003h 11.22.ab.44.55.66.77.88 : : 3.2.2 full match with mask mode in the full match with mask mode, data can be masked in entry units, and the data that completely matches is searched. in this mode, 4k entry data can be used, and the mask register is valid. to use the full match with mask mode, set the signal line as shown in table 3-1 (or set the mode register), and write the search data to the search data register. write the mask data that masks the search data to the mask data register. this must be completed before the search data is written to the search data register. each bit of the search data register is compared or ignored, depending on the value of the bit of the mask data register at the same bit position. a bit of the mask data register that is set to 1 is compared with the corresponding bit of the search data register; a bit of the mask register that is reset to 0 is not compared with the corresponding bit of the search data register but ignored. the search data is compared with a 64-bit value of 4k words of memory cells. the data of memory cells at addresses 0000h to 0fffh are masked by the data of memory cells at 1000h to 1fffh. if a match data is found, one clock after the search data was written to the search data register in the normal mode (two clocks after in the ff mode), the hit signal is asserted active. the address of the match data is output to had12 to had0 if enhit_b is set to 0. the timing to output the hit address can be delayed by inserting wait_b.
data sheet s13650ej5v0ds 16 pd98421 example to search data in table 3-4 from data in table 3-5 the value of the search data register is ignored when bits 24 to 31 and 8 to 15 are searched from the value of the mask data register. data of 0000h is masked by the mask of 1000h and is not compared when bits 48 to 63 are searched. in this way, the data of 0001h is the match data because of the relationship between each data and mask. the match address is 0001h. the value of 1003h is exactly the same as the value of the search data register, but it is not used as the match data because this area is used as the mask data area in the full match with mask mode. table 3-4. example of search data search data register mask data register 11.22.33.44.55.66.77.88 ff.ff.ff.ff.00.ff.00.ff table 3-5. example of data address data address mask 0000h 11.22.33.44.55.66.77.bb 1000h 00.00.ff.ff.ff.ff.ff.ff. 0001h 11.22.aa.44.55.66.77.88 1001h ff.ff.00.ff.ff.ff.ff.ff 0002h cc.22.33.44.55.66.77.88 1002h ff.ff.ff.ff.ff.ff.00.00 0003h 99.aa.bb.cc.dd.ee.ff.00 1003h 11.22.33.44.55.66.77.88 : : : :
data sheet s13650ej5v0ds 17 pd98421 3.2.3 longest prefix match mode the longest prefix match mode can search the data with the longest match in the search data, by means of masking in entry units. the 4k-word area of addresses 0000h to 0fffh is used as an entry data area, and 1000h to 1fffh are used as a mask data area corresponding to the entry data. in the longest prefix match mode, contiguous bits, starting from the least significant bit, must be masked as the mask data (refer to 2.1.2 full match with mask/longest prefix match mode ). the mask data register is valid, and the masking set by this register is valid for all the entries. the contiguous bits of the mask data register must be also masked, starting from the least significant bit. to connect two or more pd98421 chips, the values of the mask data registers of all the chips must be the same. searching in the longest prefix match mode is started by setting the signal lines as shown in table 3-1 (or setting the mode register) and writing the search data to the search data register. two clocks after the search has been started in the normal mode (four clocks after in the ff mode), the hit_b pin is asserted active. the address of the match data is output to the had12 to had0 pins if enhit_b is set to 0. the timing to output the hit address can be delayed by inserting wait_b. if two or more match data are found during the search operation, the err_b pin goes low, and the output to the had12 to had0 pins is invalid. if no match data is found, both the hit_b and err_b pins go high. the mask data that masks search data is written to the mask data register. this must be completed before the search data is written to the search data register. the search data is compared with a 64-bit value of 4k words of memory cells. the data of the memory cells at addresses 0000h to 0fffh is masked by the data of memory cells at addresses 1000h to 1fffh. unlike the other two modes, the data of a memory cell having a bit string with the longest successive match in the search data, starting from the msb, is the match data. example 1 to search with only one chip the data shown in table 3-6 is searched from the data of the memory cells shown in table 3-7. the value of the mask data register is masked after a value has been written to the search data register. because all the bits of the mask data are 1, all the bits of the search data register are compared when searched. the data stored to each memory cell is compared in the same manner as in the full match with mask mode. of the matching data, that which has the longest number of bits that match is the final match data. in this example, it is the data of 0001h.
data sheet s13650ej5v0ds 18 pd98421 table 3-6. example of search data search data register mask data register 11.22.33.44.55.66.77.88 ff.ff.ff.ff.ff.ff.ff.ff table 3-7. example of data address data address mask 0000h 11.22.33.44.00.00.00.00 1000h ff.ff.ff.ff.00.00.00.00 0001h 11.22.33.44.55.66.77.00 1001h ff.ff.ff.ff.ff.ff.ff.00 0002h 11.22.33.44.55.00.00.00 1002h ff.ff.ff.ff.ff.00.00.00 0003h 11.22.33.44.55.66.77.aa 1003h ff.ff.ff.ff.ff.ff.00.00 : : : : even when two or more pd98421 chips are connected, the data with the longest match in the search data can be searched from all the pd98421s. this can be done by connecting the smd63 to smd0 pins of all the chips. when two or more chips are connected, make sure that the values of the mask data registers of all the chips are the same. example 2 to search with two or more chips data in table 3-8 is searched from the data of the memory cells shown in tables 3-9 to 3-11. these tables show different pd98421 chips. when searching is started, 0001h of chip 1, 0002h of chip 2, and 0001h of chip 3 match as the match addresses. in this case, 0002h of chip 2 in table 3-10 has the shortest mask bit. therefore, the data of 0002h of chip 2 is the match data. at this time, only the hit_b pin of chip 2 goes low; the hit_b pins of chips 1 and 3 go high. table 3-8. search data search data register mask data register 6e.13.01.22.5f.c2.77.e8 ff.ff.ff.ff.ff.ff.ff.ff table 3-9. memory cells of chip 1 address data address mask 0000h 11.22.33.44.55.00.00.00 1000h ff.ff.ff.ff.ff.00.00.00 0001h 6e.13.01.22.5f.c2.77.00 1001h ff.ff.ff.ff.ff.ff.00.00 0002h 6e.13.01.22.00.00.00.00 1002h ff.ff.ff.ff.00.00.00.00 0003h 6f.ff.ff.ff.ff.00.00.00 1003h ff.ff.ff.ff.ff.00.00.00 : : : :
data sheet s13650ej5v0ds 19 pd98421 table 3-10. memory cells of chip 2 address data address mask 0000h 11.22.33.44.00.00.00 1000h ff.ff.ff.ff.00.00.00.00 0001h 6e.13.01.22.5f.c2.00.00 1001h ff.ff.ff.ff.ff.ff.00.00 0002h 6e.13.01.22.5f.c2.77.00 1002h ff.ff.ff.ff.ff.ff.ff.00 0003h 6d.ff.fe.ef.ff.ff.00.00 1003h ff.ff.ff.ff.ff.ff.00.00 : : : : table 3-11. memory cells of chip 3 address data address mask 0000h 6e.13.01.22.5f.c2.aa.00 1000h ff.ff.ff.ff.ff.ff.ff.00 0001h 6e.13.01.22.5f.c2.00.00 1001h ff.ff.ff.ff.ff.ff.00.00 0002h 6e.13.01.22.5f.bf.00.00 1002h ff.ff.ff.ff.ff.ff.00.00 0003h 6e.13.01.22.61.01.00.00 1003h ff.ff.ff.ff.ff.ff.00.00 : : : : 3.2.4 other points to be noted ? do not change the mode by using the mem, full, and fmsk pins in a mode that operates with two or more clock cycles. similarly, do not change a12 to a0. remark modes that operate with two or more clock cycles in normal mode : longest prefix match mode in ff mode: memory/register read, full match mode, full match with mask mode, and longest prefix match mode ? write to the nop register for one or more clocks when changing the operation and the search mode. ? create an external circuit in which reset_b becomes low after power application. ? after releasing reset, input at least 2 clk or more nop commands continuously. ? when a search operation is stopped temporarily using ce (ce_b) during a continuous search operation, almost the same power is consumed as during a search operation. in this case, shift into no-operation mode by writing to the nop register or inserting a wait. ? when performing a continuous search operation in the normal mode, make the total search frequency 66% or below.
data sheet s13650ej5v0ds 20 pd98421 cautions when connecting multiple pd98421s the output load capacitance in the ac characteristics described later is 50 pf, so if the load capacitance exceeds 50 pf through the connection of multiple devices, the delay amount shown in the figure below must be added as an output delay. reference this delay value when designing external circuits. the delay value in the figure is only that of the output buffer. note also that the level at which output of the delay value is determined is v ih (2.0 v) for the rising delay and v il (0.8 v) for the falling delay. 5.00e-09 0 25 50 75 100 125 150 4.50e-09 4.00e-09 3.00e-09 2.00e-09 1.00e-09 0.00e+00 5.00e-10 3.50e-09 2.50e-09 1.50e-09 load exceeding 50 pf [pf] output buffer load dependence (typ.) @ rising delay delay [s] 5.00e-09 0 25 50 75 100 125 150 4.50e-09 4.00e-09 3.00e-09 2.00e-09 1.00e-09 0.00e+00 5.00e-10 3.50e-09 2.50e-09 1.50e-09 load exceeding 50 pf [pf] output buffer load dependence (typ.) @ falling delay delay [s]
data sheet s13650ej5v0ds 21 pd98421 4. electrical specifications all the rated values below are when the pd98421 is cooled at a wind velocity of 2 m/s. absolute maximum ratings parameter symbol conditions rating unit supply voltage v dd ? 0.5 to +4.6 v input voltage v i ? 0.5 to +v dd + 0.5 v i/o voltage v io ? 0.5 to +v dd + 0.5 v operating ambient temperature t a 0 to 70 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions parameter symbol conditions min. typ. max. unit supply voltage v dd 3.15 3.3 3.45 v input voltage, high v ih1 other than clk, reset_b 2.0 v dd v v ih2 clk, reset_b 2.4 v dd v input voltage, low v il1 other than clk, reset_b 0 0.8 v v il2 clk, reset_b 0 0.4 v operating ambient temperature t a cooled at a wind velocity of 2 m/s or more 070 c dc characteristics (t a = 0 to +70c, v dd = 3.3 v 0.15 v) parameter symbol conditions min. typ. max. unit output voltage, high v oh i oh = ? 4.0 ma 2.4 v output voltage, low v ol i ol = 8.0 ma 0.4 v f clk = 33 mhz (normal mode) 1150 ma operating current i dd note f clk = 50 mhz (ff mode) 1150 ma input leakage current i li v i = 0 v to v dd 10 a output leakage current i lo v io = 0 v to v dd output: not selected 10 a pull-up resistance (had and smd pins) r pu v i = 0 v 25 50 150 k ? note when performing a continuous search operation in the normal mode, make the total search frequency 66% or below.
data sheet s13650ej5v0ds 22 pd98421 capacitance parameter symbol conditions min. typ. max. unit input capacitance c in v in = 0 v, f = 1 mhz 10 pf output capacitance c out v in = 0 v, f = 1 mhz 10 pf i/o capacitance c i/o v in = 0 v, f = 1 mhz 10 pf ac characteristics (t a = 0 to 70c, v dd = 3.3 v 0.15 v) all the values below are at an output load capacitance of 50 pf. clk input parameter symbol conditions min. typ. max. unit normal mode 30 125 ns clk cycle time t cyclk ff mode 20 125 ns normal mode 13 ns clk high-level width t clkh ff mode 9 ns normal mode 13 ns clk low-level width t clkl ff mode 9 ns clk rise time t clkr 3ns clk fall time t clkf 3ns 2.4 v 1.5 v 0.4 v t cyclk t clkh t clk 0.4 v (max.) 2.4 v (min.) v ppclk t clkr t clkf reset input parameter symbol conditions min. typ. max. unit reset_b low-level width t wrstl t cyclk 2ns
data sheet s13650ej5v0ds 23 pd98421 ce and ce_b operations parameter symbol conditions min. typ. max. unit ce data valid time t dcedata 10 ns ce_b data valid time ce had valid time t dcehad 10 ns ce_b had valid time ce err_b valid time t dceerr 10 ns ce_b err_b valid time ce smd valid time t dcesmd 10 ns ce_b smd valid time ce data float time t fcedata 10 ns ce_b data float time ce had float time t fcehad 10 ns ce_b had float time ce err_b float time t fceerr 10 ns ce_b err_b float time ce smd float time t fcesmd 10 ns ce_b smd float time
data sheet s13650ej5v0ds 24 pd98421 search/memory operations (1/2) parameter symbol conditions min. typ. max. unit address setup time t sa 4ns address hold time t ha 4ns data setup time t sdata 4ns data hold time t hdata 4ns ce, ce_b setup time t sce 4ns ce, ce_b hold time t hce 3ns mem setup time t smem 3ns mem hold time t hmem 3ns we_b setup time t swe 3ns we_b hold time t dwe 3ns wait_b setup time t swait 3ns wait_b hold time t hwait 3ns full, fmsk setup time t smode 4ns full, fmsk hold time t hmode 3ns normal mode 26 ns delay time from clk to data t ddata ff mode 10 ns clk data invalid time t ddatax normal mode 4 ns we_b data valid time t dwedata 10 ns we_b data float time t fwedata 10 ns oe_b data valid time t doedata 10 ns oe_b data float time t foedata 10 ns enhit_b had valid time t dehhad 10 ns enhit_b had float time t fehhad 10 ns enhit_b err_b valid time t deherr 10 ns enhit_b err_b float time t feherr 10 ns normal mode 26 ns clk had valid time t dhad ff mode 10 ns normal mode 26 ns clk had float time t fhad ff mode 10 ns clk had invalid time t dhadx 5ns normal mode 26 ns clk hit_b delay time t dhit ff mode 10 ns clk hit_b invalid time t dhitx 5ns normal mode 26 ns clk err_b valid time t derr ff mode 10 ns normal mode 26 ns clk err_b float time t ferr ff mode 10 ns clk err_b invalid time t derrx 5ns smd setup time t ssmd 2ns
data sheet s13650ej5v0ds 25 pd98421 search/memory operations (2/2) parameter symbol conditions min. typ. max. unit smd hold time t hsmd 3ns normal mode 26 ns clk smd low-level valid time t dsmdl1 note ff mode 10 ns clk smd low-level valid time t dsmdl2 note normal mode 12 ns clk smd high-level valid time t dsmdh1 normal mode 2 13 ns clk smd high-level valid time t dsmdh2 ff mode 2 10 ns clk smd float time t fsmd 210ns note the smd low-level valid time satisfies either the t dsmdl1 or t dsmdl2 value. (1) memory access (normal mode) a[12:0] full,fmsk t clkh t cyclk t fceerr t fehhad memory write address 1 memory write data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] clk hi-z ce has timing identical to ce_b. t hmem t feherr t deherr t dcehad t swe t hwe t smem t sdata t ha t sa memory read address 1 had[12:0] t clkl t fcehad t dehhad t ddata t fcedata t fwedata t doedata t foedata t dwedata t dceerr t sce t hce t hdata t swait hi-z memory read data 1 memory read data 2 t ddata t ddatax t hwait nop memory read address 2 nop memory write address 2 memory write address 3 memory write data 2 memory write data 3 t dcedata remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 26 pd98421 (2) memory access (ff mode) t clkh t cyclk t fceerr t fehhad memory write address 1 memory write data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z ce has timing identical to ce_b. t hmem t feherr t deherr t dcehad t swe t hwe t smem t sdata t ha t sa memory read address 1 full,fmsk had[12:0] t clkl t fcehad t dehhad t ddata t fwedata t dwedata t dceerr t sce t hce t hdata t swait hi-z t hwait nop nop memory write address 2 memory write address 3 memory write data 2 memory write data 3 memory read data 1 remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 27 pd98421 (3) i/o access (normal mode) t clkh t cyclk full,fmsk t fceerr t fehhad i/o write address 1 i/o write data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z ce has timing identical to ce_b. t hmem t feherr t deherr t dcehad t swe t hwe t smem t sdata t ha t sa i/o read address 1 had[12:0] t clkl t fcehad t dehhad t ddata t fcedata t fwedata t doedata t foedata t dwedata t dceerr t sce t hce t hdata t swait hi-z i/o read data 1 i/o read data 2 t ddata t ddatax t hwait nop i/o read address 2 nop i/o write address 2 i/o write address 3 i/o write data 2 i/o write data 3 t dcedata remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 28 pd98421 (4) i/o access (ff mode) i/o write data 3 i/o write data 2 t cyclk t clkh t fceerr t fehhad i/o write address 1 i/o write data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z ce has timing identical to ce_b. t hmem t feherr t deherr t dcehad t swe t hwe t smem t sdata t ha t sa i/o read address 1 full,fmsk had[12:0] t clkl t fcehad t dehhad t ddata t fwedata t dwedata t dceerr t sce t hce t hdata t swait hi-z t hwait nop nop i/o write address 2 i/o write address 3 i/o read data 1 remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 29 pd98421 (5) full match search (normal mode) nop 00h t fhad t cyclk search data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z hi-z ce has timing identical to ce_b. t hmem t derrx t dhad t swe t hwe t smem t sdata t ha t sa full,fmsk had[12:0] t clkh t clkl t feerr t hdata t swait hi-z t hwait search data 2 search data 3 search data 4 search data 5 search data 6 search data 7 low high full match search mode t smode t hmode hit address 1 t dhadx t dhit t dhad t dhitx t derr t deherr t feherr t dehhad t fehhad hit address 5 hit address 6 hit address 7 remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 30 pd98421 (6) full match search with mask (normal mode) nop 00h t fhad t cyclk search data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z hi-z ce has timing identical to ce_b t hmem t derrx t dhad t swe t hwe t smem t sdata t ha t sa full,fmsk had[12:0] t clkh t clkl t feerr t hdata t swait hi-z t hwait search data 2 search data 3 search data 4 search data 5 search data 6 search data 7 low high full match with mask t smode t hmode hit address 1 t dhadx t dhit t dhad t dhitx t derr t deherr t feherr t dehhad t fehhad hit address 5 hit address 6 hit address 7 remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 31 pd98421 (7) longest prefix match search (normal mode) low nop 00h t fhad t cyclk search data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z ce has timing identical to ce_b. t hmem t derrx t dhad t swe t hwe t smem t sdata t ha t sa full,fmsk had[12:0] t clkh t clkl t feerr t hdata t swait hi-z t hwait low high longest prefix match search mode t smode t hmode hit address 1 t dhadx t dhit t dhad t dhitx t derr search data 1 search data 1 t dsmdl1 t dsmdl2 temp data 1 t fsmd t dsmdh all high t fsmd temp data 2 all high temp data 3 remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 32 pd98421 (8) full match search (ff mode) nop 00h t fhad t cyclk search data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z hi-z ce has timing identical to ce_b. t hmem t derrx t dhad t swe t hwe t smem t sdata t ha t sa full,fmsk had[12:0] t clkh t clkl t feerr t hdata t swait t hwait search data 2 search data 3 search data 4 low high t smode t hmode hit address 1 t dhadx t dhit t dhad t dhitx t derr full match search mode low remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 33 pd98421 (9) full match search with mask (ff mode) t fhad t cyclk search data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] clk hi-z hi-z t hmem t derrx t dhad t swe t hwe t smem t sdata full,fmsk had[12:0] t clkh t clkl t feerr t hdata t swait t hwait search data 2 search data 3 search data 4 low high t smode t hmode hit address 1 t dhadx t dhit t dhad t dhitx t derr full match with mask search mode nop 00h a[12:0] t ha t sa ce has timing identical to ce_b. low remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 34 pd98421 (10) longest prefix match search (ff mode) t hdata 00h t fhad t cyclk search data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z ce has timing identical to ce_b. t hmem t dhad t swe t hwe t smem t sdata t ha t sa full,fmsk had[12:0] t clkh t clkl t feerr t swait hi-z t hwait nop low high longest prefix match search mode t smode t hmode hit address 1 t dhadx t dhit t dsmdl1 temp data 1 t fsmd t dsmdh all high t fsmd low remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 35 pd98421 (11) full match search (normal mode, insertion wait) nop 00h t fhad t cyclk search data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z hi-z ce has timing identical to ce_b. t hmem t derrx t dhad t swe t hwe t smem t sdata t ha t sa full,fmsk had[12:0] t clkh t clkl t feerr t hdata t swait t hwait search data 2 search data 3 search data 4 low high full match search mode t smode t hmode hit address 1 t dhadx t dhit t dhad t dhitx t derr t dhad hit address 1 t feerr low remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 36 pd98421 (12) longest prefix match search (normal mode, insertion wait) t hdata 00h t cyclk search data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z ce has timing identical to ce_b. t hmem t dhad t swe t hwe t smem t sdata t ha t sa full,fmsk had[12:0] t clkh t clkl t feerr t swait hi-z t hwait low high longest prefix match search mode t smode t hmode hit address 1 t dhadx t dhit t dsmdl1 t dsmdl2 search data 2 nop t dhad hit address 2 t dhadx t dhit temp data 1 t fsmd t dsmdh all high t fsmd temp data 2 all high low remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 37 pd98421 (13) search memory access search (normal mode) memory write address 1 nop 00h 00h 00h nop t cyclk search data 1 err_b smd[63:0] enhit_b hit_b wait_b oe_b we_b mem ce_b data[63:0] a[12:0] clk hi-z ce has timing identical to ce_b. t hmem t dhad t swe t hwe t smem t sdata t ha t sa full,fmsk had[12:0] t clkh t clkl t feerr t hdata t swait hi-z t hwait nop search data 2 memory data 1 search data 3 low high full match search mode t smode t hmode longest prefix search mode full match with mask hit address 1 t dhadx t dhit hit address 2 temp data 1 all high low remark ce is the inversion of ce_b.
data sheet s13650ej5v0ds 38 pd98421 5. recommended soldering conditions the pd98421 should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual ( c10535e ). for soldering methods and conditions other than those recommended below, contact your nec sales representative. surface-mount type ? ? ? ? pd98421f1-ga1: 240-pin plastic fbga (16 16) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 230 c, time: 30 seconds max. (at 210 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir30-103-2 note after opening a dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period.
data sheet s13650ej5v0ds 39 pd98421 6. package drawing p240f1-80-ga1 b x 0.08 y 0.10 y 1 0.20 sd 0.40 se 0.40 zd 1.2 ze 1.2 0.50 + 0.05 ? 0.10 240-pin plastic fbga (16x16) item millimeters d 16.00 0.10 d 1 15.4 w 0.20 e 0.80 e 16.00 0.10 e 1 15.4 a 1.31 0.15 a 1 0.35 0.10 a 2 0.96 index mark se sd a zd a1 e a2 s wb s wa b a s vutrpnmlk jhgfedcba 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 4-c1.0 4-r0.3max. s y s y 1 25 s x 240- b ab m d d 1 e e 1 ze
data sheet s13650ej5v0ds 40 pd98421 [memo]
data sheet s13650ej5v0ds 41 pd98421 [memo]
data sheet s13650ej5v0ds 42 pd98421 [memo]
data sheet s13650ej5v0ds 43 pd98421 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd98421 m8e 00. 4 the information in this document is current as of january, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a pa rticular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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